The following commonly assigned patent/patent applications are hereby incorporated herein by reference:
This invention relates generally to the field of electronic devices and more particularly to a method for forming a embedded FLASH memory circuit with reduced processing steps.
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
The density of the microelectronic devices on the semiconductor substrate may be increased by decreasing spacing between each of the various semiconductor devices. This decrease in spacing allows a larger number of such microelectronic devices to be formed on the semiconductor substrate. As a result, the computing power and speed of the semiconductor component may be greatly improved.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells with each cell having a floating gate transistor. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each cell is a floating gate transistor having a source, drain, floating gate, and a control gate. The floating gate uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line.
Embedding FLASH memory circuits in CMOS logic circuits (embedded FLASH) is finding increasing usage in building more complex integrated circuits such as digital signal processors for applications such as hard disk controllers. Traditionally, in CMOS integrated circuit fabrication, the polysilicon gates of both the NMOS and PMOS transistors were doped n-type with phosphorous through diffusion or ion implantation with no additional photolithography masks. The shrinking dimensions of the transistors in current use in CMOS integrated circuits have led to the gate of the NMOS transistors being doped n-type with this dopant being blocked from entering the gates of the PMOS transistors using a photolithographic pattern and masking step. The gates of the PMOS transistors are implanted p-type during the formation of the source and drain regions of the PMOS transistors. This process results in the proper threshold voltage in both the NMOS and PMOS transistors.
In the FLASH memory array, a continuous source line is often used to increase circuit packing density. This continuous source line is formed using a self-aligned source (SAS) process. Here, the isolation regions between the source regions of adjacent FLASH memory cell transistors are removed using a photolithography and etch process. Photolithography is used to form a patterned resist film and the exposed oxide isolation is removed using a oxide etch process. A continuous source line is then formed using ion implantation of n-type dopant species with the photoresist acting as an implant mask.
In the fabrication of embedded FLASH circuits, the CMOS transistors are masked during the SAS process and then processed separately after the formation of the FLASH memory cells and the continuous source line. This is mainly due to the inability to simultaneously etch doped and undoped polysilicon to form CMOS transistor gate structures. This masking and separate processing of the CMOS and FLASH portions of an embedded integrated circuit results in a complex process requiring many photolithographic masking levels which add tremendous cost to the process.
Accordingly, a need has arisen for a simplified process to form embedded FLASH integrated circuits. The present invention provides method that accomplishes this through a reduction in number of masking levels and improved etching processes. The method comprises: forming a photoresist film on a semiconductor substrate; patterning said photoresist film to expose a source line region in a FLASH memory array and a polycrystalline silicon film region in a CMOS circuit wherein said polycrystalline silicon film region will be used to form a gate electrode of a NMOS transistor; and simultaneously implanting said exposed source line region and said exposed polycrystalline silicon film region with a dopant ion species.